What is a System Modelling Language (SysML)?

SysML is a standard approach for the first-phase developments of full-stack hardware and software architectures. It allows the modelling of a system in an abstract representation with blocks and connection between these blocks.

As part of WP1 of the MASTERLY project, RWTH Aachen develops a library of SysML diagrams. A main package of diagrams contains the hardware at different levels intended for use in a generic human-robot collaboration scenario. Later, further specific diagrams will be derived from the generic ones for each of the three Masterly use-cases.

This state-of-the-art approach is deployed from the beginning of the MASTERLY project to ensure a standardized development format for all the stages of the project.